Qualcomm High Bandwidth Compute aims to compete with High Bandwidth Flash and Memory by stacking LPDDR just above the…
- Qualcomm introduces High Bandwidth Compute (HBC) memory architecture
- It leverages a hybrid design stacking LPDDR memory in a 3D space, leveraging multiple layers to essentially replace what the current generation of High Bandwidth Memory (HBM4) does
- The move, which makes use of Qualcomm's extensive experience with LPDDR, is not only power-efficient but also offers massive amounts of bandwidth and up to 768GB of stacked memory for AI workloads
Qualcomm is reigniting its Data Center ambitions, building on its expertise as a chip designer that excels in the low-power compute segment by focusing on an entirely new architecture: High Bandwidth Compute (HPC).
The solution is a hybrid take on existing LPDDR memory that Qualcomm has successfully stacked in 3D vertical space, not unlike the industry-standard High Bandwidth Memory (HBM) and its latest iteration, HBM4, while delivering significant power savings along the way.
The move is possible by Qualcomm offering a near-memory...
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