Government issues notifications for six pillars of Semicon 2.0
Union Minister for Electronics and Information Technology Ashwini Vaishnaw on Monday outlined the government’s plans for the next phase of India’s semiconductor programme as notifications for all six pillars of the Semicon 2.0 scheme were issued.
The scheme will provide fiscal and infrastructure support across the semiconductor value chain, covering chip design, fabrication, packaging, equipment and materials, research and development, and talent development.
Semicon 2.0 will operate across six pillars: design; machines and materials; setting up more fabs; strengthening the ATMP/OSAT industry; research and development; and talent development.
The design pillar covers semiconductor IPs, chips, system-on-chips and modules for strategic and commercial applications, as well as a deployment-linked incentive for semiconductor IPs, chips and SoCs.
The machines and materials pillar covers the semiconductor manufacturing ecosystem. The fabs pillar includes silicon semiconductor wafer fabs, compound semiconductor, photonics, sensors and discrete semiconductor fabs, as well as display fabs.
The fourth pillar covers...
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