AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027
- AMD EPYC 9006 "Venice" offers mammoth 256-core, 512-thread configuration that incorporates up to 1GB of L3 cache and PCI-E 6.0 and 16 DDR5 memory channels under the hood
- It's the first time AMD's EPYC lineup sees high core count CPUs push past the 5GHz barrier
- AMD is claiming a win by stating that its newest EPYC CPU offers the "most agents per watt, per dollar, per rack"
AMD's newly-announced 6th Gen EPYC 9006 "Venice" seems to be a genuine silicon milestone (the first x86 server CPU on a 2nm-class node, up to 256 cores and 512 threads) which sees the company aim to secure its position in the AI data center CPU market.
The launch comes at a time when AMD has caught Intel on the back foot but finds its position threatened in turn by Nvidia's Vera CPU, which it touts as a faster, more efficient alternative...
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