AMD's 256 core Epyc Venice enters production on TSMC's 2nm node

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First look: AMD's next-generation Epyc Venice server chip has begun its production ramp on TSMC's N2 node, the foundry's new 2nm-class process. That move brings a 256-core server part onto one of the most advanced nodes at a time when data centers are straining to add capacity for AI and other agentic workloads.

Venice is a 6th-gen Epyc chip based on the Zen 6 core architecture and targeted at dense data center workloads. AMD is claiming more than a 70% improvement in overall performance and efficiency versus the current Epyc Turin chips, along with more than a 30% increase in thread density.

The extra performance is not just from adding cores; AMD is also leaning on IPC improvements, higher clocks, and changes in the core and uncore design to close the gap. The...

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