3D Stacking Tech Packs 4x More Compute Power Into Tiny Chips
We have effectively hit the physical limit of traditional transistor scaling using silicon. If transistors are packed together any more tightly, weird effects like quantum tunneling will cause our chips to misbehave. So, as with construction projects in a crowded city, the only way to go is up. Three-dimensional chips, in which layers of silicon are stacked on top of one another, are now enabling chip designers to pack more compute power into smaller footprints.
However, there is an obvious problem with this approach: stacked chips are thicker. Thick chips don’t mix well with our obsession with ultra-thin devices, so we need a solution to this problem. A group led by researchers at the Pohang University of Science and Technology believes that they may have the solution. They have developed a technology that enables the stacking of ten or more ultra-thin layers inside a single chip.
The transfer printing and...
Copyright of this story solely belongs to hackster.io. To see the full text click HERE
